1. Field of the Invention
This invention relates to a whole chip electrostatic discharge, ECD, circuit and method.
In particular, this invention relates to distributing the circuit of this invention next to each input/output pad in order to provide parallel ESD current discharge paths.
2. Description of Related Art
FIG. 1 shows a prior art input/output protection circuit. This protection circuit is placed next to each input/output (I/O) pad. Each protection circuit, like the one shown in FIG. 1, is used to protect only one I/O pad. If one of the I/O pads is zapped with high voltage or high current, the electrostatic discharge, ESD, current 170 only flows through the protection circuit adjacent to the zapped I/O pad. The circuit in FIG. 1 is connected to the supply voltage Vcc 190 and to Vss 150 or ground. The circuit includes a p-channel metal oxide semiconductor field effect transistor PMOS FET device 110 and an n-channel metal oxide semiconductor field effect transistor NMOS FET device 120. It also includes a bipolar junction transistor 180 and a resistor 160.
U.S. Pat. No. 6,344,412 (Ichikawa, et al.) “An Integrated ESD protection method and system” describes a method and a system for protecting integrated circuits from electrostatic discharge damage.
U.S. Pat. No. 6,262,873 (Pequignot, et al.) “A Method for Providing ESD Protection for an Integrated Circuit” discloses a method for providing electrostatic protection for integrated circuits.
U.S. Pat. No. 6,218,704 (Brown, et al.) “ESD Protection Structure and Method” discloses an integrated circuit structure and method for electrostatic discharge protection for chips.